Core - XEOS: API Reference [ XS-Labs ]

XEOS_HAL_PIC_GetRegister Top

Gets the register number for a PIC register

uint8_t XEOS_HAL_PIC_GetRegister( XEOS_HAL_PIC_Controller c, XEOS_HAL_PIC_Register r );

Parameters

• c
  The PIC
• r
  The PIC register

Return value

The register number

XEOS_HAL_PIC_IRQLineMasked Top

Checks if an IRQ line is masked

bool XEOS_HAL_PIC_IRQLineMasked( XEOS_HAL_PIC_IRQ irq );

Parameters

• irq
  The IRQ line to unmask (0-15)

Return value

True if the IRQ line is masked, otherwise false

XEOS_HAL_PIC_MaskIRQLine Top

Masks an IRQ line

void XEOS_HAL_PIC_MaskIRQLine( XEOS_HAL_PIC_IRQ irq );

Parameters

• irq
  The IRQ line to mask (0-15)

XEOS_HAL_PIC_ReadData Top

Reads data from a PIC

uint8_t XEOS_HAL_PIC_ReadData( XEOS_HAL_PIC_Controller c );

Parameters

• c
  The PIC

Return value

The data read

XEOS_HAL_PIC_Remap Top

Remaps the PIC (Programmable Interrupt Controller)

void XEOS_HAL_PIC_Remap( uint8_t masterBase, uint8_t slaveBase );

Parameters

• masterBase
  The base IRQ number for the master controller
• slaveBase
  The base IRQ number for the slave controller

XEOS_HAL_PIC_SendCommand Top

Sends a command to a PIC

void XEOS_HAL_PIC_SendCommand( XEOS_HAL_PIC_Controller c, uint8_t command );

Parameters

• c
  The PIC
• command
  The command to send

XEOS_HAL_PIC_SendData Top

Sends data to a PIC

void XEOS_HAL_PIC_SendData( XEOS_HAL_PIC_Controller c, uint8_t data );

Parameters

• c
  The PIC
• data
  The data to send

XEOS_HAL_PIC_SendEOI Top

Sends EOI (End Of Interrupt)

void XEOS_HAL_PIC_SendEOI( XEOS_HAL_PIC_Controller c );

Parameters

• c
  The PIC

XEOS_HAL_PIC_UnmaskIRQLine Top

Unmasks an IRQ line

void XEOS_HAL_PIC_UnmaskIRQLine( XEOS_HAL_PIC_IRQ irq );

Parameters

• irq
  The IRQ line to unmask (0-15)

XEOS_HAL_PIC_Controller Top

Programmable Interrupt Controller

typedef enum { XEOS_HAL_PIC_Controller1 = 0x00, XEOS_HAL_PIC_Controller2 = 0x01 } XEOS_HAL_PIC_Controller;

Constants

• XEOS_HAL_PIC_Controller1
  Master PIC
• XEOS_HAL_PIC_Controller2
  Slave PIC

XEOS_HAL_PIC_ICW1 Top

PIC Initialization Command Word (ICW) 1

typedef enum { XEOS_HAL_PIC_ICW1None = 0x00, XEOS_HAL_PIC_ICW1IC4 = 0x01, XEOS_HAL_PIC_ICW1SNGL = 0x02, XEOS_HAL_PIC_ICW1ADI = 0x04, XEOS_HAL_PIC_ICW1LTIM = 0x08, XEOS_HAL_PIC_ICW1Init = 0x10 } XEOS_HAL_PIC_ICW1;

Constants

• XEOS_HAL_PIC_ICW1None
  No value
• XEOS_HAL_PIC_ICW1IC4
  PIC expects to recieve IC4 during initialization
• XEOS_HAL_PIC_ICW1SNGL
  Only one PIC in system
• XEOS_HAL_PIC_ICW1ADI
  CALL address interval is 4
• XEOS_HAL_PIC_ICW1LTIM
  Operate in Level Triggered Mode
• XEOS_HAL_PIC_ICW1Init
  PIC needs to be initialized

XEOS_HAL_PIC_ICW4 Top

PIC Initialization Command Word (ICW) 4

typedef enum { XEOS_HAL_PIC_ICW4None = 0x00, XEOS_HAL_PIC_ICW4UPM = 0x01, XEOS_HAL_PIC_ICW4AEOI = 0x02, XEOS_HAL_PIC_ICW4MS = 0x04, XEOS_HAL_PIC_ICW4BUF = 0x08, XEOS_HAL_PIC_ICW4SFNM = 0x10 } XEOS_HAL_PIC_ICW4;

Constants

• XEOS_HAL_PIC_ICW4None
  No value
• XEOS_HAL_PIC_ICW4UPM
  80x86 mode
• XEOS_HAL_PIC_ICW4AEOI
  Performs EOI (End Of Interrupt) on the last interrupt acknowledge pulse
• XEOS_HAL_PIC_ICW4MS
  Selects buffer master
• XEOS_HAL_PIC_ICW4BUF
  Operates in buffered mode
• XEOS_HAL_PIC_ICW4SFNM
  Special fully nested mode

XEOS_HAL_PIC_IRQ Top

IRQ lines

typedef enum { XEOS_HAL_PIC_IRQ0 = 0x00, XEOS_HAL_PIC_IRQ1 = 0x01, XEOS_HAL_PIC_IRQ2 = 0x02, XEOS_HAL_PIC_IRQ3 = 0x03, XEOS_HAL_PIC_IRQ4 = 0x04, XEOS_HAL_PIC_IRQ5 = 0x05, XEOS_HAL_PIC_IRQ6 = 0x06, XEOS_HAL_PIC_IRQ7 = 0x07, XEOS_HAL_PIC_IRQ8 = 0x08, XEOS_HAL_PIC_IRQ9 = 0x09, XEOS_HAL_PIC_IRQ10 = 0x0A, XEOS_HAL_PIC_IRQ11 = 0x0B, XEOS_HAL_PIC_IRQ12 = 0x0C, XEOS_HAL_PIC_IRQ13 = 0x0D, XEOS_HAL_PIC_IRQ14 = 0x0E, XEOS_HAL_PIC_IRQ15 = 0x0F } XEOS_HAL_PIC_IRQ;

Constants

• XEOS_HAL_PIC_IRQ0
  IRQ line 0 (master PIC)
• XEOS_HAL_PIC_IRQ1
  IRQ line 1 (master PIC)
• XEOS_HAL_PIC_IRQ2
  IRQ line 2 (master PIC)
• XEOS_HAL_PIC_IRQ3
  IRQ line 3 (master PIC)
• XEOS_HAL_PIC_IRQ4
  IRQ line 4 (master PIC)
• XEOS_HAL_PIC_IRQ5
  IRQ line 5 (master PIC)
• XEOS_HAL_PIC_IRQ6
  IRQ line 6 (master PIC)
• XEOS_HAL_PIC_IRQ7
  IRQ line 7 (master PIC)
• XEOS_HAL_PIC_IRQ8
  IRQ line 8 (slave PIC)
• XEOS_HAL_PIC_IRQ9
  IRQ line 9 (slave PIC)
• XEOS_HAL_PIC_IRQ10
  IRQ line 10 (slave PIC)
• XEOS_HAL_PIC_IRQ11
  IRQ line 11 (slave PIC)
• XEOS_HAL_PIC_IRQ12
  IRQ line 12 (slave PIC)
• XEOS_HAL_PIC_IRQ13
  IRQ line 13 (slave PIC)
• XEOS_HAL_PIC_IRQ14
  IRQ line 14 (slave PIC)
• XEOS_HAL_PIC_IRQ15
  IRQ line 15 (slave PIC)

XEOS_HAL_PIC_Register Top

PIC register

typedef enum { XEOS_HAL_PIC_RegisterCommand = 0x00, XEOS_HAL_PIC_RegisterStatus = 0x01, XEOS_HAL_PIC_RegisterData = 0x02, } XEOS_HAL_PIC_Register;

Constants

• XEOS_HAL_PIC_RegisterCommand
  PIC command register
• XEOS_HAL_PIC_RegisterStatus
  PIC status register
• XEOS_HAL_PIC_RegisterData
  PIC data register

__XEOS_HAL_PIC_H__ Top

#define __XEOS_HAL_PIC_H__