CPU identification (cpuid instruction)
void XEOS_HAL_CPU_CPUID(
uint32_t info,
uint32_t *eax,
uint32_t *ebx,
uint32_t *ecx,
uint32_t *edx );
Disables PAE (Physical Address Extension)
void XEOS_HAL_CPU_DisablePAE(
void );
Enables PAE (Physical Address Extension)
void XEOS_HAL_CPU_EnablePAE(
void );
Gets the CPU brand name string
const char * XEOS_HAL_CPU_GetBrandName(
void );
The CPU brand name string
Gets the content of the Control Register 0 (CR0)
uint32_t XEOS_HAL_CPU_GetCR0(
void );
The content of CR0
Gets the content of the Control Register 1 (CR1)
uint32_t XEOS_HAL_CPU_GetCR1(
void );
The content of CR1
Gets the content of the Control Register 2 (CR2)
uint32_t XEOS_HAL_CPU_GetCR2(
void );
The content of CR2
Gets the content of the Control Register 3 (CR3)
uint32_t XEOS_HAL_CPU_GetCR3(
void );
The content of CR3
Gets the content of the Control Register 4 (CR4)
uint32_t XEOS_HAL_CPU_GetCR4(
void );
The content of CR4
Gets the CPU vendor ID string
const char * XEOS_HAL_CPU_GetVendorID(
void );
The CPU vendor ID string
Checks if the CPU supports a feature
bool XEOS_HAL_CPU_HasFeature(
XEOS_HAL_CPUInfos_Feature feature );
True if the feature is supported, otherwise false
Checks if the interrupts are enabled
bool XEOS_HAL_CPU_InterruptsEnabled(
void );
True if the interrupts are enabled, otherwise false
Loads the Global Descriptor Table (GDT) pointer
void XEOS_HAL_CPU_LoadGDT(
void *p );
Loads the Interrupt Descriptor Table (IDT) pointer
void XEOS_HAL_CPU_LoadIDT(
void *p );
Checks if PAE (Physical Address Extension)
bool XEOS_HAL_CPU_PAEEnabled(
void );
True if PAE is enabled, otherwise false
Checks if paging is enabled
bool XEOS_HAL_CPU_PagingEnabled(
void );
True if paging is enabled, otherwise false
Gets the content of a Model Specific Register (MSR)
uint64_t XEOS_HAL_CPU_RDMSR(
uint32_t id );
The MSR value
Sets the content of the Control Register 0 (CR0)
void XEOS_HAL_CPU_SetCR0(
uint32_t value );
Sets the content of the Control Register 1 (CR1)
void XEOS_HAL_CPU_SetCR1(
uint32_t value );
Sets the content of the Control Register 2 (CR2)
void XEOS_HAL_CPU_SetCR2(
uint32_t value );
Sets the content of the Control Register 3 (CR3)
void XEOS_HAL_CPU_SetCR3(
uint32_t value );
Sets the content of the Control Register 4 (CR4)
void XEOS_HAL_CPU_SetCR4(
uint32_t value );
Generates a software interrupt
void XEOS_HAL_CPU_SoftwareInterrupt(
uint8_t n );
Writes a value into a Model Specifi Register (MSR)
void XEOS_HAL_CPU_WRMSR(
uint32_t id,
uint64_t value );
x86-64 registers
typedef struct {
uint64_t rax;
uint64_t rbx;
uint64_t rcx;
uint64_t rdx;
uint64_t rsi;
uint64_t rdi;
uint64_t r8;
uint64_t r9;
uint64_t r10;
uint64_t r11;
uint64_t r12;
uint64_t r13;
uint64_t r14;
uint64_t r15;
uint64_t rsp;
uint64_t rbp;
} XEOS_HAL_CPU_Registers;
Structure representing the x86-64 registers. For i386, the same typedef is available, but with a different layout.
i386 registers
typedef struct {
uint32_t eax;
uint32_t ebx;
uint32_t ecx;
uint32_t edx;
uint32_t esi;
uint32_t edi;
uint32_t esp;
uint32_t ebp;
} XEOS_HAL_CPU_Registers;
Structure representing the i386 registers. For x86-64, the same typedef is available, but with a different layout.
CPU features
typedef enum {
XEOS_HAL_CPUInfos_FeatureFPU = 0x000,
XEOS_HAL_CPUInfos_FeatureVME = 0x001,
XEOS_HAL_CPUInfos_FeatureDE = 0x002,
XEOS_HAL_CPUInfos_FeaturePSE = 0x003,
XEOS_HAL_CPUInfos_FeatureTSC = 0x004,
XEOS_HAL_CPUInfos_FeatureMSR = 0x005,
XEOS_HAL_CPUInfos_FeaturePAE = 0x006,
XEOS_HAL_CPUInfos_FeatureMCE = 0x007,
XEOS_HAL_CPUInfos_FeatureCX8 = 0x008,
XEOS_HAL_CPUInfos_FeatureAPIC = 0x009,
XEOS_HAL_CPUInfos_FeatureSEP = 0x00B,
XEOS_HAL_CPUInfos_FeatureMTRR = 0x00C,
XEOS_HAL_CPUInfos_FeaturePGE = 0x00D,
XEOS_HAL_CPUInfos_FeatureMCA = 0x00E,
XEOS_HAL_CPUInfos_FeatureCMOV = 0x00F,
XEOS_HAL_CPUInfos_FeaturePAT = 0x010,
XEOS_HAL_CPUInfos_FeaturePSE36 = 0x011,
XEOS_HAL_CPUInfos_FeaturePN = 0x012,
XEOS_HAL_CPUInfos_FeatureCLFlush = 0x013,
XEOS_HAL_CPUInfos_FeatureDTS = 0x015,
XEOS_HAL_CPUInfos_FeatureACPI = 0x016,
XEOS_HAL_CPUInfos_FeatureMMX = 0x017,
XEOS_HAL_CPUInfos_FeatureFXSR = 0x018,
XEOS_HAL_CPUInfos_FeatureSSE = 0x019,
XEOS_HAL_CPUInfos_FeatureSSE2 = 0x01A,
XEOS_HAL_CPUInfos_FeatureSS = 0x01B,
XEOS_HAL_CPUInfos_FeatureHT = 0x01C,
XEOS_HAL_CPUInfos_FeatureTM = 0x01D,
XEOS_HAL_CPUInfos_FeatureIA64 = 0x01E,
XEOS_HAL_CPUInfos_FeaturePBE = 0x01F,
XEOS_HAL_CPUInfos_FeaturePNI = 0x100,
XEOS_HAL_CPUInfos_FeaturePCLMulQDQ = 0x101,
XEOS_HAL_CPUInfos_FeatureDTES64 = 0x102,
XEOS_HAL_CPUInfos_FeatureMonitor = 0x103,
XEOS_HAL_CPUInfos_FeatureDSCPL = 0x104,
XEOS_HAL_CPUInfos_FeatureVMX = 0x105,
XEOS_HAL_CPUInfos_FeatureSMX = 0x106,
XEOS_HAL_CPUInfos_FeatureEST = 0x107,
XEOS_HAL_CPUInfos_FeatureTM2 = 0x108,
XEOS_HAL_CPUInfos_FeatureSSSE3 = 0x109,
XEOS_HAL_CPUInfos_FeatureCID = 0x10A,
XEOS_HAL_CPUInfos_FeatureFMA = 0x10C,
XEOS_HAL_CPUInfos_FeatureCX16 = 0x10D,
XEOS_HAL_CPUInfos_FeatureXTPT = 0x10E,
XEOS_HAL_CPUInfos_FeaturePDCM = 0x10F,
XEOS_HAL_CPUInfos_FeaturePCID = 0x111,
XEOS_HAL_CPUInfos_FeatureDCA = 0x112,
XEOS_HAL_CPUInfos_FeatureSSE41 = 0x113,
XEOS_HAL_CPUInfos_FeatureSSE42 = 0x114,
XEOS_HAL_CPUInfos_FeatureX2APIC = 0x115,
XEOS_HAL_CPUInfos_FeatureMOVBE = 0x116,
XEOS_HAL_CPUInfos_FeaturePOPCNT = 0x117,
XEOS_HAL_CPUInfos_FeatureTSCDeadLine = 0x118,
XEOS_HAL_CPUInfos_FeatureAES = 0x119,
XEOS_HAL_CPUInfos_FeatureXSave = 0x11A,
XEOS_HAL_CPUInfos_FeatureOSXSave = 0x11B,
XEOS_HAL_CPUInfos_FeatureAVX = 0x11C,
XEOS_HAL_CPUInfos_FeatureF16C = 0x11D,
XEOS_HAL_CPUInfos_FeatureRDRND = 0x11E,
XEOS_HAL_CPUInfos_FeatureHypervisor = 0x11F
} XEOS_HAL_CPUInfos_Feature;